Technical Papers
Reducing Physical Verification Cycle Time
As a result, ensuring that the original design intent is maintained is increasingly difficult. Identifying these new defect mechanisms puts a new burden on physical verification runtimes. Worse still, due to the complexity of these effects, debugging a problem through layout modifications without generating some new problem is more challenging, requiring more verification iterations than ever before. Given these impacts, the time required to iterate from design to a physically- and electrically-clean layout in these designs can rapidly overrun production schedules and delivery dates.
Clearly, new verification strategies are needed. All aspects of the physical verification cycle, from physical verification run times to the time required to identify, understand and debug design violations, must be re-evaluated. Engineers must be able to identify new complex physical interactions and characterize all physical, topological and electrical failure mechanisms associated with new process. Maintaining real-world production schedules, however, means increasing the number of iterations required to validate fixes while decreasing the total runtimes for each component. Design violations must be presented as clearly and efficiently as possible, to reduce debugging time, and approaches that reduce the time required to re-verify the impact of changes to a design must be implemented.
Calibre provides the most comprehensive and forward-looking functionality for performing DRC, LVS and DFM simulations. Through hyperscaling technology and the ability to utilize specialized cell processor architecture, Calibre ensures the fastest possible runtimes. The advanced debugging features of Calibre RVE presents all failure mechanisms to the user in a simple interface, directly within the engineer's design environment. With incremental verification and debug, Calibre lets engineers validate the impacts of design modifications without waiting for DRC runs to complete. Together, these capabilities offer the ability to dramatically reduce the total physical verification cycle time.
Variability Aware Modeling and Characterization in Standard Cell in 45 nm CMOS with Stress Enhancement Technique
Gate density is ultimately increased to 2100 kGates/mm2 by pushing the critical design rules without increasing the circuit margin in 45 nm technology. Layout dependences for stress enhanced MOSFET including contact positioning, 2nd neighboring poly effect, and bent diffusion are accurately modeled for the first time. With the constructed design flow, gate length change of 2.8% to +3.6% and Idsat change of 10% to +14% are removed from uncertain margin in 45 nm corner libraries.
Enhancing Process Model Stability & Predictability Using SEM Image Contours
The process model is a major factor affecting the quality of the Model Based Optical Proximity Correction (OPC). A better process model directly leads to better OPC, hence better yield and more profit. The traditional way in calibrating these process models is using CD measurements at sample locations in the test chip. However, the use of Scanning Electron Microscope (SEM) image contours for process model calibration and optimization has been recently introduced in an attempt to build more predictable models. In this study, we characterize the traditional flow models versus the contour calibrated models and study the effect of using different combinations and weighting schemes on the quality of the resulting process models, its stability and its ability to correctly predict the process.
Fast and Simple Modeling of Non-Rectangular Transistors
As CMOS feature size scales down to 65nm and below, challenges for device and circuit manufacturability are emerging. As commonly seen in real designs, devices with distorted gate shapes and rough line-edges are manufactured despite the applications of aggressive resolution enhancement techniques (RET). It has been shown that such irregular gates could introduce significant extra leakage current. Existing tools and device models cannot handle non-rectangular geometries. Therefore, it is critical that a modeling flow capable of handling such irregular devices is developed and smoothly integrated into the post-lithography delay and leakage circuit analysis process. Previously proposed methods either model an irregular transistor as two different rectangular devices, one for on and the other for off state analyses; or they are difficult to be implemented. In this paper, we propose a new modeling approach that serves as a fast and simple solution to this problem and overcomes these drawbacks. We found that by adjusting both gate length and width of the equivalent device, a single equivalent rectangular device can be determined. Through TCAD and SPICE simulation experiments, we demonstrate that our model can accurately capture both on and off currents of the modeled non-rectangular gate device. The average error of our modeling approach is 1.6% for Ion and 7.5% for Ioff.
Toward Faster OPC Convergence: Advanced Analysis for OPC Iterations and Simulation Environment
Achieving faster Turn-Around-Time (TAT) is one of the most attractive objectives for the silicon wafer manufacturers despite the technology node they are processing. This is valid for all the active technology nodes from 130nm till the cutting edge technologies. There have been several approaches adopted to cut down the OPC simulation runtime without sacrificing the OPC output quality, among them is using stronger CPU power and Hardware acceleration which is a good usage for the advancing powerful processing technology. Another favorable approach for cutting down the runtime is to look deeper inside the used OPC algorithm and the implemented OPC recipe. The OPC algorithm includes the convergence iterations and simulation sites distribution, and the OPC recipe is in definition how to smartly tune the OPC knobs to efficiently use the implemented algorithm. Many previous works were exposed to monitoring the OPC convergence through iterations and analyze the size of the shift per iteration, similarly several works tried to calculate the amount of simulation capacity needed for all these iterations and how to optimize it for less amount. The scope of the work presented here is an attempt to decrease the number of optical simulations by reducing the number of control points per site and without affecting OPC accuracy. The concept is proved by many simulation results and analysis. Implementing this flow illustrated the achievable simulation runtime reduction which is reflected in faster TAT. For its application, it is not just runtime optimization, additionally it puts some more intelligence in the sparse OPC engine by eliminating the headache of specifying the optimum simulation site length.
Double Dipole RET Investigation for 32 nm Metal Layers
For 32 nm test chips, aggressive resolution enhancement technology (RET) was required for 1x metal layers to enable printing minimum pitches before availability of the final 32 nm exposure tool. Using a currently installed immersion scanner with 1.2 numerical aperture (NA) for early 32 nm test chips, one of the RET strategies capable of resolving the minimum pitch with acceptable process latitude was dipole illumination. To avoid restricting the use of minimum pitch to a single orientation, we developed a double-expose/single-develop process using horizontal and vertical dipole illumination. To enable this RET, we developed algorithms to decompose general layouts, including random logic, interconnect test patterns, and SRAM designs, into two mask layers: a first exposure (E1) of predominantly vertical features, to be patterned with horizontal dipole illumination; and, a second exposure (E2) of predominantly horizontal features, to be patterned with vertical dipole illumination. We wrote this algorithm into our OPC program, which then applies sub-resolution assist features (SRAFs) separately to the E1 and E2 masks, coordinating the two to avoid problems with overlapping exposures. This was followed by two-mask OPC, using E1 and E2 as mask layers and the original layout (single layer) as the target layer. In this paper, we describe some of the issues with decomposing layout by orientation, issues that arise in SRAF application and OPC, and some approaches we examined to address these issues.
Convergence-based OPC Method for Dense Simulations
As the process of migration of Optical process correction (OPC) recipes continues to go from sparse to dense computations, a run time effectiveness issue persists to remain for huge structures that exist in some metal and active layers designs. Even for 45 and 32 nm technology nodes, some polygons might be several microns in width consuming a vast amount of simulation time and order of magnitudes more than sparse simulations to converge. Practically, this problem is pronounced, which is usually the case, when the design comprises these huge structures and other small critical ones that needs many iterations and careful tuning to converge. And thus, a considerable amount of run time will be wasted while applying these sophisticated recipes on big structures that could originally converge within few iterations using a simple recipe. In this context, a convergence-based dense OPC recipe is proposed to deal with designs that have both types of structures. The basic idea is to check convergence prior starting next iteration and skip the rest of the iterations if the whole simulated frame has converged within a predefined tolerance. Also, a reasonable way to define tolerances is explored.
Compute resource management and turn around time control in mask data prep
With each new process technology node chip designs increase in complexity and size, and mask data prep flows require more compute resources to maintain the desired turn around time (TAT) at a low cost. Securing highly scalable processing for each element of the flow – geometry processing, resolution enhancements and optical process correction, verification and fracture – has been the focal point so far. The utilization for different flow elements depends on the operation, the data hierarchy and the device type. This paper introduces a dynamic utilization driven compute resource control system applied to large scale parallel computation environment. The paper will analyze performance metrics TAT and throughput for a production system and discuss trade-offs of different parallelization approaches in data processing regarding interaction with dynamic resource control. The study focuses on 65nm and 45nm designs.
Characterizing OPC model accuracy versus lens induced polarization effects in hyper NA immersion lithography
Immersion lithography is extending the lifetime of optical lithography by enabling numerical aperture (NA) greater than unity. Along with scanner hardware improvements, modeling of hyper-NA lithography systems for optical proximity correction (OPC) is also continuing to be necessary in improving photolithography capability. With the use of hyper-NA immersion lithography and polarized illumination, the assumption of scalar optical pupil in optical system modeling may no longer be valid. To fully describe the transmission of any polarization state through the optical system, Jones matrix is necessary. It has been shown that Jones matrix can be described as a combination of apodization loss, birefringence, diattenuation, scalar phase aberrations, and rotation effects. In this work, the impact of such effects on calibration and accuracy of OPC models is characterized in terms of the model fit quality, model predictability, and changes to OPC results.
AIMS-45 image validation of contact hole patterns after inverse lithography at NA 1.35
The AIMS™-45, when used in scanner mode, can emulate image intensity as seen in resist on the wafer at scanner illumination conditions. We show that this feature makes AIMS™-45 well-suited to inspect patterns treated with inverse lithography. We have used an inverse lithography technique by Mentor Graphics, to treat a random contact hole layout (drawn at minimal pitch 115nm) for imaging at NA 1.35. The combination of the dense 115nm pitch and available NA of 1.35 makes Quasar illumination necessary, and the inverse lithography treatment automatically generated optimal (model-based) Assist Features (AF) for all geometries in the design. The mask, after inverse lithography treatment, has CH patterns with numerous AF of different sizes and orientations, and is a challenge for both mask making and mask inspection. We have inspected the inverse lithography masks with the model-based AF using an AIMS™-45 aerial image measurement tool, and compare the results of the AIMS™-45 to wafer data obtained after exposure on an ASML XT:1900i. A first benefit AIMS™-45 is that the most meaningful quantity (image in resist) is generated without the intermediate steps of doing multiple reticle SEM measurements followed by extensive simulation. A second point of interest is that the AIMS™-45 generates image intensities, which allows a direct validation of the intensity-driven inverse litho conversion. Both features prove the value of the AIMS™-45 for inspecting inverse litho masks and geometries.
Accelerate OPC convergence with new iteration control methodology
A dilemmatic trade-off that all OPC engineers are facing everyday is the convergence of the OPC result and the control of the OPC iteration times. Theoretically, infinite times of OPC iterations are needed to achieve a convergent and stable correction result. But actually there should always be a cut-off for the iteration time, for turnaround- time is always an important criteria for IC fabs. But considering the design layout becomes more complicated and pattern density becomes higher with the shrinkage of the critical dimension, fragmentation control during the OPC procedure is also becoming more and more sophisticated. Thus, to achieve a convergent correction result for all OPC fragments within limited correction iteration times now becomes a big challenge to OPC engineers. This work presents our study in a new OPC iteration control methodology. It can help to find an algorithm that always converges, and reduce the excessive use of parameter setting, commands and other involvement by the user. With this, we can reduce the run time required to obtain a convergent OPC solution.