Layout Verification
| Calibre nmDRC and Calibre nmLVS are the market share leaders in physical verification. Its high scaling hierarchical processing delivers the fastest turn around times in the industry. | |
| Calibre's adoption as the sign-off standard at all of the top foundries ensures accurate results for first time success tape-outs. With integrations to all the industry leading physical design creation tools, Calibre's Results | |
Viewing Environment (RVE) reduces the length times required in debugging complex issues like shorts, antennas and density from days or hours to minutes. Together, these and the other benefits of Calibre ensure the fastest cycle time through physical verification to tape out, and ultimately working silicon.
Events
Meeting the Critical Challenges of IC Implementation
Learn about the evolution of Mentor's comprehensive Design-to-Silicon IC implementation solution.
AAA and Advanced DFM—Collaboration for Success
Design-for-Manufacturing (DFM) requires a close working relationship between a foundry and its EDA partners to ensure that customers can create competitive designs with the highest possible yield.
Approaching Yield in the Nanometer Age: The Framework for an Extensible DFM Methodology
This online tutorial goes into detail on these new technical challenges and solutions within both the business and historical context of the IC design and manufacturing process. It shows the importance of the fabless model as part of a more holistic DFM methodology, and includes demonstrations of what the new tools look like.
Calibre Design-to-Silicon Platform Workshop
Learn how to leverage the superior performance and capacity of the Calibre design-to-silicon platform, a comprehensive suite of tools designed to address the complex handoff between design and manufacturing
