Testbench Creation & Automation

• Constrained-random stimulus generation capabilities in SystemVerilog or SystemC greatly improve productivity
• Powerful testbenches allow the creation of many more test vectors than would be possible with directed test techniques
• SystemVerilog testbenches can be used to drive VHDL designs as well as SystemVerilog designs
• SystemVerilog and SystemC testbench-specific features allow the creation of reusable testbenches and race-free interactions with the DUT