Scalable Verification Online Events

Functional verification challenges continue as designs grow in size and complexity. Verification environments also continue to advance as verification techniques enabled by standard hardware verification languages become main stream. Collecting and analyzing information from these broad set of tools and techniques becomes more critical to meeting product schedules and project success. The Questa verification platform enables the best verification techniques.

Assertion Based Verification, or ABV, is a powerful methodology which increases verification productivity through improved bug detection/isolation as well as shortening the time required to debug design failures. This seminar is designed help design and verification engineers adopt ABV for VHDL or Verilog designs. The Questa Verification Library offers a prebuilt set of checkers and monitors that can help users quickly experience the benefit of ABV. The SystemVerilog language enables several new verification methodologies which target increased verification productivity. This seminar provides examples of both SystemVerilog assertions and utilization of the Questa Verification Library.

Freescale's next generation communications processors include an integrated security engine. As more commerce moves on-line, open, 'best-effort' IP infrastructure is no longer sufficient. An increasing percentage of network traffic is being protected by security protocols such as IPSec, SSL, SSH, and these security protocols make use of computationally intensive cryptographic algorithms. Without hardware acceleration, these cryptographic algorithms would consume too much system packet processing bandwidth, bringing network traffic to a crawl. Freescale's MPC8548E secure communication processor allows system designers to offer high performance, secure systems, at a fraction of the cost of discrete solutions.

Mentor Graphics Seamless® hardware/software co-verification is available today to help you accelerate your PowerQUICC processor-based systems to market. Seamless is proven to reduce risk in embedded system development by performing system integration months before a hardware prototype is available. Seamless co-verification is an ideal environment for analyzing system throughput and identifying performance bottlenecks.

Designing today’s powerful products put stress on verification environments.  ModelSim extensive integrated support of VHDL, Verilog and SystemC provide a rich opportunity for debug productivity.  Each of these languages offer specific debug needs and ModelSim has proven technology that continues to evolve.  Features like debugging Verilog deltas, process debugging, tracing through source code, comparing results of waveform files, vcd stimulus.  These are a few of the features that will be featured during this comprehensive technical debug seminar.

In addition, this seminar will have a brief presentation and demo of our Codelink tool. Codelink provides source-level debug for code executing on RTL processor models like ARM’s design simulation model (DSM). Codelink is an integral part of the ModelSim GUI giving ModelSim synchronous HW/SW debug capability. Codelink delivers highly interactive debug both during and post simulation.

These archived online seminars focus on the methodology, tools and infrastructure you'll need to handle those large verification projects.

By architecting Questa and the Advanced Verification Methodology (AVM) to provide revolutionary productivity and predictability benefits in an evolutionary way, Mentor Graphics is uniquely positioned to help you achieve your goals, both technically and organizationally.

Today's complex projects demand that you take advantage of advanced techniques like constrained-random stimulus, functional coverage and assertions, and Questa and the AVM give you the jumpstart you need to include them in your arsenal.

By integrating our 0-in formal verification and clock-domain crossing (CDC) solutions, as well as our Questa Power-Aware solution, a new universe of unparallelled productivity is at your fingertips.

When combined with Questa's unique Verification Management facilities, you now have a way to track every aspect of your verification activities back to your Verification Plan, analyze your results in a logical way, and know that you’ve properly addressed every requirement.

This 45 minute multimedia presentation will walk the audience through various strategies for adopting an Advanced Verification. We will examine the different components including:

• Assertion-Based Verification
• Constrained-Random Verification
• Coverage-Driven Verification
• Testbench Automation

We will show how these techniques can be applied both incrementally to existing verification environments and in a proactive manner to build an infrastructure capable of taking full advantage of these powerful concepts. We will discuss various aspects of the verification problem, and show how the Questa verification platform provides the tool infrastructure required to support the methodology.

Presented by Walter Gude - Senior Application Engineer

This 60 minute multimedia presentation will go into the specific features that ModelSim PE and SE provide above what is available in the silicon vendor version of ModelSim commonly provided by Actel, Altera, Atmel and Xilinx.

If you are seeking increased functionality or just need a lot more performance to get your designs done, then this online seminar is for you.

To support synthesis and place-and-route, ModelSim Designer automatically manages your project files, easing the downstream transition to the synthesis and place-and-route tools of your choice. Connection of these additional tools is easy, giving FPGA designers control of simulation, design creation, synthesis, and place-and route from a single cockpit.

ModelSim Designer is also very extensible with lots of options available like code coverage, SWIFT interface, and a profiler to identify your performance bottlenecks.

This 30 minute multimedia presentation provides an overview of ModelSim Designer and demonstrates how to Mange the entire FGPA Design process and import and analyze Existing HDL code.

Clocking issues are the second leading cause of silicon respins. In today's multi-clock designs, errors relating to the management of clock-domain crossing (CDC) signals are difficult to find with traditional verification -- resulting in functional errors in silicon.

This web seminar will examine why CDC signals cause problems for verification, how they can be identified, managed and verified using automated RTL analysis combining formal and simulation techniques. We will discuss the methodology to facilitate effective CDC verification.

As SoC design complexity and configurability increases, the need for combining IP efficiently from various sources is a requirement. The development and enablement of standards in platform-based design and IP reuse helps to reduce costs while improving product ease-of-use and integration flexibility. Mentor Graphics Platform Express enables designers to rapidly create and verify platform-based SoC designs by automating complex, tedious, error-prone design creation, and IP integration and verification steps. The ARM PrimeXsys Platform ease-of-use is enhanced by the robustness of the Platform Express system design methodology and the multi-vendor SPIRIT standard tool and IP support. Platform-based design based on these robust methodologies, IP-architecture and design-standards shaves months off aggressive product development cycles and allows designers to focus on product differentiating tasks.

Traditional SoCs use a processor for the control plane and IP logic blocks for most data-path functions. With the advent of small, fast configurable cores, processors and firmware are replacing some of the dedicated logic for audio and video data transform functions. Firmware in the data path demands new verification methods which support the co-simulation of logic and firmware in order to fully prove correct functionality. 

Tensilica's answer comes in the form of configurable processor flexibility. Configurable and pre-configured processor cores can perform on-chip processing while providing software programmability and RTL processing speeds. They also provide a nearly infinite number of software-compatible processors that span a wide performance and area range. 

Mentor Graphics Seamless product has been named the premier co-verification tool for Tensilica’s new Diamond Standard series of processor cores. Seamless provides designers with a virtual platform to debug hardware/software integration issues while increasing simulation throughput, thereby allowing designers to quickly validate that the system hardware and software are functionally correct before prototypes are manufactured. 

This online seminar walks you through the basics of these two product lines, explaining how they work in conjunction with one another to provide a complete solution to SoC design complexity.